Solid state memories (SSMs) provide an efficient mechanism for storing and transferring data in a wide variety of applications, such as hand-held portable electronic devices. Individual memory cells within such memories can be volatile or non-volatile, and can store data by the application of suitable write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read access operation by applying suitable read currents and sensing voltage drops across the cells.
Some SSM cell configurations employ a memory element coupled to a channel based switching device such as a metal oxide semiconductor field effect transistor (MOSFET). The switching device provides selective access to the memory element during read and write operations. Examples of memory cells with this type of memory element-switching device arrangement include, but are not limited to, volatile dynamic random access memory (DRAM), non-volatile resistive random access memory (RRAM), and non-volatile spin-torque transfer random access memory (STRAM).
While operable, a limitation with the use of MOSFETs and other types of switching devices in a memory cell is the areal extent (size) of such devices. A horizontal MOSFET layout is often used in which the associated drain and source regions are placed adjacent one another in a base substrate, with the channel region extending horizontally therebetween. The memory element is formed above either the source or the drain.
Horizontal MOSFETs may require a minimum size of about 4F2 where F is the minimum feature dimension of the associated manufacturing process (e.g., F=70 nm, etc.). Since this is significantly larger than the areal size of many types of memory elements, the switching device size can be a limiting factor in achieving greater areal densities in a memory array.
Some recent semiconductor memory designs have proposed a stacked memory cell arrangement whereby the memory element and the transistor are vertically aligned as a pillar, or stack, above a base substrate. In a stacked memory cell, the drain and source regions are located one above the other, with the channel region extending vertically therebetween. While advantageously promoting an enhanced areal data density, it can be difficult to form the pillar structure of the vertical transistor so that the transistor can operate optimally.